Memories and registers are exposed to radiation that can introduce soft errors in both the memory bit cells and the flip flops. This causes the content of the memory or the flip flops to be corrupted, which often causes device failure. The probability of such a soft error corruption in flip flop increases with increased integration and smaller manufacturing technologies. The percentage of FIT rate (Failure in Time over billion seconds) that is directly related to such soft error corruption in the flip flops is on the rise.
Conventional solutions to this problem include adding ECC (Error Correction Code) to the memory bit cells. This requires extra hardware logic to detect and correct errors on every read to the memory. This logic adds to the latency of memory accesses causing an overall degradation in performance. Conventional solutions for errors in discrete registers includes using specially designed and radiation hardened flip flops or using flip flops with ECC or parity built into them. Each of these conventional solutions adds gates to the flip flop and has a negative impact on the area and speed of the design.